Hardware Implementation of Streaming Logarithm Computing Unit for Fixed-Point Data

The work aims to create hardware implementation of the streaming computing unit for logarithm calculation in fixed-point. Logarithms are widely used in telecommunications, particularly in radio intelligence to convert power spectrum values to decibels for further processing of spectrum data, e.g. for radio signals detection, range-finding, or direction-finding. For spectrum analysis of high sampling rate wideband signals, it is expedient to utilize hardware computing units for streaming logarithm calculation, implemented inside FPGA or ASIC chips. The market offers a large amount of IP cores for logarithm calculation in floating point. Floating-point calculation units offer a high dynamic range but also consume a large number of hardware resources that could diminish the maximum clock frequency of devices. In the proposed work, different approaches for logarithm calculating are considered, including CORDIC, Taylor series, and table-based methods. Authors proposed a mathematical model and architecture of streaming computing unit for base 2 logarithm calculation in fixed-point that can be easily adapted to any other base, simply multiplying the result by a constant. The proposed computing unit utilizes a table-based approach and counting leading zeroes in the argument. Based on the mathematical model, the high-level computational model in MATLAB® Simulink® was created. All the components of the mentioned model are compatible with HDL Coder. The proposed MATLAB® Simulink® model is parameterizable, one can set word and fraction width for input/output data, and memory size for table-based part. Using HDL Coder, Verilog HDL implementation for the proposed logarithm computing unit was synthesized. Utilizing HDL Verifier authors created the testbench in Verilog language for the verification of created computing unit on RTL level of abstraction based on reference data collected during simulation in Simulink. Running generated testbench in ModelSim simulator for one million clock cycles proved that there are no differences in operation between the Simulink Model and generated HDL design. The authors were synthesized HDL implementation of the created computing unit in Quartus Prime for the Stratix IV FPGA chip to evaluate the hardware cost of the proposed solution. The developed logarithm calculation unit was compared to the existing CORDIC, Taylor series, and table-based implementations in terms of calculation error and hardware costs. Additionally, for comparison purposes the authors created a hardware implementation for the base 2 logarithm calculation unit in a single-precision floating-point. During the evaluation of the calculation error, the double-precision floating-point logarithm computing unit from Simulink was chosen as the source for reference results. The comparison showed that created computing unit provides less calculation error compared to the existing fixed-point solutions, requires fewer hardware resources for implementation and can operate on higher clock frequencies. All the created models and source codes are open for utilization and can be downloaded from GitHub.